摘要

Recent studies have shown that manufacturing costs and design complexities may delay the widespread use of high-/metal gate nanoscale CMOS technologies. This implies that traditional (non-high-kappa/non-metal gate) ultra-thin oxide technologies will remain active due to economic factors for longer periods of time. Direct tunneling is a significant source of MOSFET gate current in these technologies. Its presence fundamentally alters MOSFET functionality by invalidating the simplifying design assumption of infinite gate resistance. Analog circuit solutions to its problems do not exist in the literature. This paper proposes design solutions that attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional ultra-thin oxide CMOS technologies. The proposed solutions require only ultra-thin oxide devices and are investigated in a 65-nm CMOS technology with a nominal V-DD of 1 V and a physical oxide thickness of 1.25 nm.

  • 出版日期2011-4