摘要

A subharmonically injection-locked phase-locked loop (SIPLL) using a pulsewidth-calibrated loop is presented. The injection timing and the pulsewidth of the injected pulse are calibrated to tolerate the process variations. This SIPLL is fabricated in a 40-nm CMOS process. The measured output frequency ranges from 0.4 to 1.6 GHz. Its power is 1.49 mW for a supply of 1.1 V at 1.6 GHz. The root-mean-square jitter is 2.29 ps.