All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs

作者：Hasan Syed Rafay^*; Belanger Normand; Savaria Yvon; Ahmad M Omair

来源：Integration, the VLSI Journal, 2011, 44(1): 22-38.

DOI：10.1016/j.vlsi.2010.05.003

• SoC
• Multiple clock domains
• GALS
• Synchronizers
• Inter-module communications

High-performance clocking of intellectual property (IP) modules, within a skew budget, is becoming difficult in deep sub-micron technologies. In this work, we propose a novel and all-digital synchronous design method for point-to-point communications, using two stages of interfacing registers and locally delayed clock with phase adjustments. This design is free from synchronizers and clock-data mismatch problems. Moreover, communicating modules run at frequencies which are virtually independent of the clock skew. We also provide a comprehensive case-wise mathematical analysis to facilitate design automation for synthesizing such designs as standard cells. An overall improvement in skew tolerance of up to n times (where n is the number of registers used), when compared to conventional designs, is achieved when the skew orientation is known and n/2 times if the skew orientation is unknown. Improvement in skew tolerance is validated using gate level simulations with the 0.18 mu m TSMC CMOS technology. A prototype implementation of the proposed design using a Virtex-II Pro FPGA from Xilinx validates the claim that such designs allow a fast module to communicate with a slow module without constraining their frequencies.

• 出版日期2011-1