Finite element analysis of thermal stress for different Cu interconnects structure

作者：Wang Ying^*; Ji Feng-li; Gao Song-song

来源：Microelectronics Reliability, 2012, 52(11): 2856-2860.

DOI：10.1016/j.microrel.2012.05.011

• MIGRATION RELIABILITY
• COPPER INTERCONNECTS
• DIELECTRIC SLOTS
• K INTERCONNECTS
• TEMPERATURE
• VIAS

Thermal stress behavior of various Cu/low-k dual damascene Cu interconnects structure is investigated in this article. Finite element analysis software ANSYS is applied to simulate the thermal stress distribution in the Cu interconnects with stress control layer (SCL), to identify the thermal stress of Cu interconnects with via gouging different depth into the underlying metal M1 and to study the thermal stress of Cu interconnects with dielectric slot. The simulation results conclude that the thermal stress of Cu interconnects is reduced by introducing stress control layer (SCL) between metal-level inter-layer dielectric (ILD) film and via-level ILD film. The thermal stress at the interface of Cu/via decreases with increasing via gouging depth, so void nucleation sites appear in Cu line M1, away from via. Cu line with dielectric slot has lower hydrostatic stress at the Cu cap/via interface than that without dielectric slot.

• 出版日期2012-11
• 单位哈尔滨工程大学