A novel obstacle-aware multiple fan-out symmetrical clock tree synthesis

作者：Liu, Meng^*; Zhang, Zhiwei; Sun, Wenqin; Wang, Donglin

来源：IEICE Electronics Express, 2017, 14(20): 20170935.

DOI：10.1587/elex.14.20170935

• symmetrical clock tree
• multiple fan-out
• matching algorithm
• buffer insertion
• obstacle-aware placement and routing

Clock tree design plays a critical role in improving chip performance and affecting power. In this paper, we propose a novel symmetrical clock tree synthesis algorithm, including tree architecture planning, matching, merging, embedding and buffer insertion. Obstacle-aware placement and routing are also integrated into the algorithm flow. By using NGSPICE simulation for benchmark circuits, our skew results decrease by 17.2% while using less than 24.5% capacitance resource compared with traditional symmetrical clock tree. Further, we also validated the algorithm in ASIC design.

• 出版日期2017-10-25
• 单位中国科学院; 中国科学院大学