摘要

Applying the recursive compensated simplified reformulated inversionless Berlekamp-Massey (rCS-RiBM) architecture, an improved Reed-Solomon (RS) decoder with the advantages of high speed and high area efficiency is proposed in this letter. The proposed architecture only includes a processing element and a compensation unit, resulting in low hardware complexity. In addition, to further increase the throughout, we adopt the technique of pipelining and new initialization. The RS (255, 239) decoder applying the rCS-RiBM architecture has been designed and synthesized with SMIC 0.18-mu m CMOS technology library. The results illustrate that our decoder needs about 13k gates (excluding FIFO stacks) and operates at 640 MHz to achieve the throughout of 5.1 Gb/s, which can be applied in optical communication systems. Meanwhile, it is at least 11% more area-efficient compared with previously reported RS decoders.