A Delay Evaluation Circuit for Analog BIST Function

作者：Lv Zhengliang^*; Yang Shiyuan; Wang Hong; Milor Linda

来源：IEICE - Transactions on Electronics, 2013, E96C(3): 393-401.

DOI：10.1587/transele.E96.C.393

• delay testing
• BIST
• analog filter
• sample-hold circuit

Process variation causes significant fluctuations in the timing performance of analog circuits, which causes a fraction of circuits to fail specifications. By testing the delay-performance, we can recognize the failed circuits during production testing. In this paper, we have proposed a low overhead and process tolerant delay evaluation circuit for built-in self test (BIST) function for analog differential circuits. This circuit contains a delay generation cell, an input differential signal generation cell, a delay matching cell, a sample-hold circuit, and a comparator. This circuit was implemented with 0.18 mu m CMOS process. Simulation results over process variation, devices mismatch and layout parasitics, but without silicon measurement, show that the accuracy in delay detection is within 5 ps. A case study was done over a feed-forward equalizer (FFE). A typical use of this circuit is testing the delay of various FIR (Finite Impulse Response) filters.

• 出版日期2013-3