A joint-LDPC decoding scheme based on retention error characteristics for MLC NAND flash memory

作者：Wei, Debao; Deng, Libao^*; Hao, Mengqi; Qiao, Liyan; Peng, Xiyuan

来源：Microprocessors and Microsystems, 2018, 60: 65-76.

DOI：10.1016/j.micpro.2018.04.001

• NAND flash memory
• LDPC
• Decoding latency
• Retention error
• Log-likelihood ratio

With the aggressive scaling and the Multi-Level Cell (MLC) technology, the reliability of NAND flash degrades seriously. Therefore, the traditional error correction schemes are becoming less and less effective. Low-Density Parity-Check (LDPC) code and soft-decision memory sensing will be more suitable in the next generation Error Correction Code (ECC) technologies for MLC NAND flash memory. However, LDPC ECC schemes have their own bottleneck due to the unacceptably long read latency during the decoding scheme. The read latency primarily includes two aspects: repeated read cycles and iterative belief-propagation decoding. Motivated by the precise probability information can improve the performance of LDPC decoding, we propose a novel Joint-LDPC (J-LDPC) scheme to reduce the decoding latency of LDPC ECC. The key idea of the proposed J-LDPC scheme is to introduce a new calculating method of probability information in a pair of shared flash pages, according to the retention error characteristics of MLC NAND flash rather than several reading operations. Through a large amount of experiments from our own hardware-software co-designed experimental platform, compared with the traditional soft-decision LDPC scheme, the proposed J-LDPC scheme can reduce the average iterations of LDPC decoder by 50% and enhance the error correction strength by 58%.

• 出版日期2018-7
• 单位哈尔滨工业大学