A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme

作者：Miura Noriyuki^*; Shidei Tsunaaki; Yuan Yuxiang; Kawai Shusuke; Takatsu Keita; Kiyota Yuji; Asano Yuichi; Kuroda Tadahiro

来源：IEEE Journal of Solid-State Circuits, 2011, 46(4): 965-973.

DOI：10.1109/JSSC.2011.2108127

• Inductive coupling
• three dimensional
• chip stacking
• low power

This paper presents a 10 fJ/bit inductive-coupling data link operating at 0.55 V supply voltage and a 135 fJ/cycle clock link at 0.7 V supply voltage. A dual-coil transmission scheme reduces the number of stacked transistors in a transmitter, enabling low-voltage and hence low-power operation. A test chip is fabricated in 65 nm CMOS whose nominal supply voltage is 1.2 V. A data rate of 1.1 Gb/s and a clock rate of 3.3 GHz, both with an error rate < 10(-12), are achieved at 0.55 V and 0.7 V supply voltage, respectively.

• 出版日期2011-4