Novel data storage for H.264 motion compensation: system architecture and hardware implementation

作者：Matei Elena^*; van Praet Christophe; Bauwelinck Johan; Cautereels Paul; de Lumley Edith G

来源：EURASIP Journal on Image and Video Processing, 2011, 2011(1): 21.

DOI：10.1186/1687-5281-2011-21

• motion compensation
• quarter-pel
• address
• memory
• H.264 decoder
• FPGA

Quarter-pel (q-pel) motion compensation (MC) is one of the features of H.264/AVC that aids in attaining a much better compression factor than what was possible in preceding standards. The better performance however also brings higher requirements for computational complexity and memory access. This article describes a novel data storage and the associated addressing scheme, together with the system architecture and FPGA implementation of H.264 q-pel MC. The proposed architecture is not only suitable for any H.264 standard block size, but also for streams with different image sizes and frame rates. The hardware implementation of a stand alone H.264 q-pel MC on FPGA has shown speeds between 95.9 fps for HD1080p frames, 229 fps for HD 720p and between 2502 and 12623 fps for CIF and QCIF formats.

• 出版日期2011