A Low-Power 64-point Pipeline FFT/IFFT Processor for OFDM Applications

作者：Yu Chu^*; Yen Mao Hsu; Hsiung Pao Ann; Chen Sao Jie

来源：IEEE Transactions on Consumer Electronics, 2011, 57(1): 40-45.

• FFT
• IFFT
• OFDM
• complex multiplier

4G and other wireless systems are currently hot topics of research and development in the communication field. Broadband wireless systems based on orthogonal frequency division multiplexing (OFDM) often require an inverse fast Fourier transform (IFFT) to produce multiple sub-carriers. In this paper, we present the efficient implementation of a pipeline FFT/IFFT processor for OFDM applications. Our design adopts a single-path delay feedback style as the proposed hardware architecture. To eliminate the read-only memories (ROM's) used to store the twiddle factors, the proposed architecture applies a reconfigurable complex multiplier and bit-parallel multipliers to achieve a ROM-less FFT/IFFT processor, thus consuming lower power than the existing works. The design spends about 33.6K gates, and its power consumption is about 9.8mW at 20MHz(1).

• 出版日期2011-2
• 单位中国科学院电工研究所