摘要
This paper presents a multiphase clock generation technique, which employs coupled oscillators and the capacitive-coupling mechanism to achieve both low-power and low-noise characteristics. An oscillator core equipped with both dual tanks and the adaptive feedback technique is proposed. To verify the concept, a four-core coupled oscillator is implemented, and an analytical model on its phase noise performance is presented using the generalized Adler's equation. The proposed four-core coupled oscillator is fabricated in a 130-nm CMOS RF SOI process. It achieves measured phase noise of -133 dBc/Hz at 1-MHz offset from 2.33 GHz. The current consumption for each oscillator core is 10 mA from a 1-V supply voltage. The figure of merit (FoM) of the eight-phase oscillator is 184.3 dBc/Hz; resulting in a per-phase FoM of 193.3 dBc/Hz.
- 出版日期2018-3