A Large sigma V-TH/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

作者：Wu Jui Jen^*; Chen Yen Huei; Chang Meng Fan; Chou Po Wei; Chen Chien Yuan; Liao Hung Jen; Chen Ming Bin; Chu Yuan Hua; Wu Wen Chin; Yamauchi Hiroyuki

来源：IEEE Journal of Solid-State Circuits, 2011, 46(4): 815-827.

DOI：10.1109/JSSC.2011.2109440

• Low supply voltage
• SRAM
• read disturb
• static noise margin
• write margin

Nanometer SRAM cannot achieve lower VDDmin due to read-disturb, half-select disturb and write failure. This paper demonstrates quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large sigma V-TH/VDD conditions. Since Z8T uses only 1T for each decoupled read-port, faster 2T differential sensing ((DS)-S-2) can be implemented within the same area as the single-ended DS8T. Thanks to (DS)-S-2, Z8T cell enables much faster R/W speed at VDDmin than DS8T. For the same VDDmin/speed, Z8T reduces the cell area by 15%. The Z8T 32 Kb macro is 14% smaller area and 53% faster than DS8T cells. Three macros were fabricated using foundry provided 65 nm low-power and 90 nm generic processes. The measured VDDmin for a 65 nm 256-row 32 Kb and a 32-row 4 Kb macro are 430 mV and 250 mV respectively. The measured VDDmin for a 90 nm 256-row 64 Kb macro is 230 mV.

• 出版日期2011-4
• 单位清华大学