A 14 b 23 MS/s 48 mW Resetting Sigma Delta ADC

作者：Lee Chun C^*; Flynn Michael P

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2011, 58(6): 1167-1177.

DOI：10.1109/TCSI.2010.2097716

• Analog-digital conversion
• high-resolution
• integrator
• Sigma Delta modulator

High-resolution, moderate-speed, calibration-free analog-to-digital converters (ADCs) are becoming increasingly difficult to design in low-voltage nanometer-scale CMOS processes. We propose an ADC architecture based on a resetting Sigma Delta modulator that achieves high resolution, despite poor component matching and poor analog transistor performance. A prototype design pipelines a second-order resetting Sigma Delta modulator and a 10 b cyclic ADC. The device achieves 14 b resolution and samples as a Nyquist converter at 23 MS/s. This calibration-free ADC achieves no missing codes, 87 dB SFDR and 11.7 b ENOB. The ADC is fabricated in 0.18 mu m CMOS and occupies a core area of 0.5 mm(2). It consumes 48 mW from a 2 V supply.

• 出版日期2011-6