摘要

This brief presents a forwarded clock receiver based on an injection-locked oscillator with a simple clock multiplication unit (CMU) to reduce the clock jitter and power consumption of the CMU. In addition, an optimal clock multiplication factor is considered to optimally multiply the clock frequency without serious degradation of the jitter correlation between data and clock. The proposed CMU employs ac coupling and a superposition technique to generate first-harmonic injection pulses. The measured power efficiency of the proposed receiver is 1.69 mW/Gb/s at a 7.4-Gb/s data rate in a 1.2 V 0.13-mu m CMOS process.

  • 出版日期2015-5

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