A Fully Integrated Digital Low-Dropout Regulator Based on Event-Driven Explicit Time-Coding Architecture

作者：Kim Doyun^*; Seok Mingoo

来源：IEEE Journal of Solid-State Circuits, 2017, 52(11): 3071-3080.

DOI：10.1109/JSSC.2017.2740269

• Capacitor less
• event driven
• low dropout (LDO)
• near-threshold voltage
• power management
• system-on-chip
• voltage regulator

This paper presents a fully integrated digital low-dropout (LDO) voltage regulator based on event-driven control architecture. The focus of the paper is to scale the off-chip output capacitor of an LDO conventionally used to compensate fast load current change. To shrink the output capacitor size, it is paramount to shorten control latency. This can be done by employing a high-speed error amplifier in analog LDO designs and by using fast clock in digital synchronous LDO designs. However, those approaches become less suitable for sub-1-V supply voltage due to the headroom problem of analog circuits and/or increase power dissipation due to the high-frequency clock. In this paper, we tackle the tradeoff between power consumption and control latency by introducing an event-driven approach. Our event-driven approach enables to perform regulation tasks only when the output voltage deviates significantly from a set point, simultaneously achieving short latency and low-power dissipation. We prototyped an event-driven digital LDO that supports 400-mu A load current at 0.5-V input and 0.45-V output voltage. The measurements show 40-mV droop voltage and 96.3% peak current efficiency with an on-chip integrated 0.4-nF output capacitor.

• 出版日期2017-11