A reconfigurable low-cost memory-efficient VLSI architecture for video scaling

作者：Wang Yangang; Peng Silong^*

来源：High Technology Letters, 2013, 19(2): 137-144.

DOI：10.3772/j.issn.1006-6748.2013.02.005

• Image quality measure
• Piecewise polynomials
• Poly phase filters
• Reconfiguration
• Resource consumption
• Run-time reconfigurable
• Verylarge-scale integration architecture (VLSI)
• Video scaling

A runtime reconfigurable very-large-scale integration (VLSI) architecture for image and video scaling by arbitrary factors with good antialiasing performance is presented in this paper. Video scaling is used in a wide range of applications from broadcast, medical imaging and high-resolution video effects to video surveillance, and video conferencing. Many algorithms have been proposed for these applications, such as piecewise polynomial kernels and windowed sinc kernels. The sum of three shifted versions of a B-spline function, whose weights can be adjusted for different applications, is adopted as the main filter. The proposed algorithm is confirmed to be effective on image scaling applications and also verified by many widely acknowledged image quality measures. The reconfigurable hardware architecture constitutes an arbitrary scaler with low resource consumption and high performance targeted for field programmable gate array (FPGA) devices. The scaling factor can be changed on-the-fly, and the filter can also be changed during runtime within a unifying framework.

• 出版日期2013