A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line

作者：Higami Yoshinobu^*; Wang Senling; Takahashi Hiroshi; Kobayashi Shin ya; Saluja Kewal K

来源：IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2017, E100D(9): 2224-2227.

DOI：10.1587/transinf.2016EDL8210

• fault diagnosis
• bridging faults
• clock lines

In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.

• 出版日期2017-9