A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization

作者：Tien Che Wei; Liu Shen Iuan^*

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 65(6): 1830-1839.

DOI：10.1109/TCSI.2017.2769721

• Phase-locked loop
• background
• minimization
• supply noise
• frequency subtractor
• supply voltage sensitivity

A digital phase-locked loop (DPLL) with the background supply voltage sensitivity minimization is presented. By using a frequency subtractor, a digital supply voltage sensitivity controller can suppress the supply voltage sensitivity of a DPLL. This DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.006 mm(2) where the supply voltage sensitivity controller occupies about 20%. The power consumption is 9.34 mW from a supply of 1.1 V wherein the supply voltage sensitivity controller consumes 840 mu W. The output frequency of the DPLL is 5 GHz with a divider ratio of 64. The minimum measured supply voltage sensitivity is -0.0044[%-f(VCO)/%-V-DD]. With a 50-mV(PP), 100-kHz sinusoidal supply noise, the peak-to-peak jitter is reduced from 41.48 to 23.15 ps, and the rms jitter is reduced from 7.26 to 3.47 ps.

• 出版日期2018-6
• 单位中国科学院电工研究所