A 58-GHz WIDE-LOCKING RANGE CMOS DIRECT INJECTION-LOCKED FREQUENCY DIVIDER USING INPUT-POWER-MATCHING TECHNIQUE

作者：Chen Chang Zhi; Hsu Wei Lun; Lin Yo Sheng^*

来源：Microwave and Optical Technology Letters, 2009, 51(3): 685-689.

DOI：10.1002/mop.24158

• CMOS
• power-matching technique
• direct injection-locked frequency-divider (DILFD)
• wide locking range

58-GHz (V-band) CMOS direct injection-locked-frequency-divider (DILFD) using technique for locking-range enhancement is reported for the first time. In an input-power-matching technique, an inductive input-matching-network is added to the gate of the NMOS switch to optimize the input-power-matching, i.e. to maximize the internal power, over the frequency band of interest. This DILFD architecture also features a very low input capacitance; therefore, high operating frequency of 58.2 GHz can be achieved. The DILFD dissipated 8.45 mW power from a 1.3 V power supply, and achieved a total locking range of 9.3 GHz (48.9-58.2 GHz; 17.4%), which is 400% higher than that (1.86 GHz (3%)) of a traditional DILFD without the input-matching-network for comparison. The chip area was only 0.585 x 0.492 mm(2) excluding the test pads.

• 出版日期2009-3