科研之友
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摘要
This work presents an all-digital pulsewidth control loop (ADPWCL). The proposed system accepts a wide range of input duty cycles and performs a fast correction to the target output pulsewidth. An all-digital delay-locked loop (DLL) with fast locking time using a simplified time to digital converter and a new differential two-step delay element is proposed. The area of the delay element is much smaller than that in conventional designs, while having the same delay range. A test chip is verified in a 0.18-mu m CMOS process. The measured duty cycle ranges from 4% to 98% with 7-bit resolution.
- 出版日期2013-3-1
- 单位中国科学院电工研究所
