Scan-Out Power Reduction for Logic BIST

作者：Wang Senling^*; Sato Yasuo; Kajihara Seiji; Miyase Kohei

来源：IEICE Transactions on Information and Systems, 2013, E96D(9): 2012-2020.

DOI：10.1587/transinf.E96.D.2012

• low power
• BIST
• multi-cycle test
• shift power

In this paper we propose a novel method to reduce power consumption during scan testing caused by test responses at scan-out operation for logic BIST. The proposed method overwrites some flip-flops (FFs) values before starting scan-shift so as to reduce the switching activity at scan-out operation. In order to relax the fault coverage loss caused by filling new FF values before observing the capture values at the FFs, the method employs multi-cycle scan test with partial observation. For deriving larger scan-out power reduction with less fault coverage loss and preventing hardware overhead increase, the FFs to be filled are selected in a predetermined ratio. For overwriting values, we prepare three value filling methods so as to achieve larger scan-out power reduction. Experiment for ITC99 benchmark circuits shows the effectiveness of the methods. Nearly 51% reduction of scan-out power and 57% reduction of peak scan-out power are achieved with little fault coverage loss for 20% FFs selection, while hardware overhead is little that only 0.05%.

• 出版日期2013-9