摘要

A digital background calibration technique to estimate the sample-time error (timing-skew) in time-interleaved ADCs is presented. Compared to the state-of-the-art, this technique requires a simpler digital block and, hence, a lower power dissipation. The proposed technique detects timing skew for each channel by means of finding zero-crossing samples with respect to a reference comparator. Simulation results show that it can effectively correct timing errors for any type of input signal up to Nyquist, and achieves a high convergence speed with a very low computational complexity.

  • 出版日期2013-8

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