摘要

In this paper, based on fractional calculus, the arbitrary-order fractor is proposed to implement the analog circuit realization of the arbitrary-order Fractional Hopfield Neural Networks (FHNNs) and the fractor-based FHNNs are first proposed to apply to the hardware security of defense against chip cloning attacks. Since the fractor is the most important circuit component needed to implement the FHNNs, the hardware achievement of the arbitrary-order fractor is the primary task and crux for the state-of-the-art application of the FHNNs to defense against chip cloning attacks. Motivated by this need, based on fractional calculus, the arbitrary-order fractor is proposed to implement the analog circuit realization of the arbitrary order FHNNs and the fractor-based FHNNs are proposed to apply to defense against chip cloning attacks. The first step is the proposal for the analog circuit realization of an arbitrary-order FHNN. In particular, the hardware achievement of the arbitrary-order net-grid-type capacitive scaling fractor of the arbitrary order FHNNs is chiefly analyzed in detail. The circuit configuration of the arbitrary-order net-grid-type scaling fractor can be achieved more convenient than any other discovered approximate implementation of the arbitrary-order fractor. Finally, the approximation performance of the arbitrary-order fractor of the FHNNs is analyzed, the arbitrary-order FHNNs are achieved by analog circuit realization, and its ability of defense against chip cloning attacks is illustrated in detail experimentally. The main contribution of this paper is the proposal for the first preliminary attempt of a feasible hardware implementation of the arbitrary-order FHNNs for defense against chip cloning attacks. Different order FHNNs can be achieved and distributed for different users, respectively. Thus, in a similar way to frequency band, order band can also be allocated efficiently that is another emerging promising electronic resource.