A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors

作者：Saito Hideaki^*; Nakajima Masayuki; Okamoto Takumi; Yamada Yusuke; Ohuchi Akira; Iguchi Noriyuki; Sakamoto Toshitsugu; Yamaguchi Koichi; Mizuno Masayuki

来源：IEEE Journal of Solid-State Circuits, 2010, 45(1): 15-22.

DOI：10.1109/JSSC.2009.2034078

• Chip stacking
• dynamic reconfiguration
• memory chip
• SoC
• 3-D IC

A dynamic-reconfigurable memory chip is fabricated, by which on-chip memories of an SoC chip can be moved to the memory chip to increase the efficiency of memory usage, and stacked on a logic chip by using three dimensional packaging technology. In the memory chip, many RAM-macros are arrayed and they are connected through two dimensional mesh network interconnects. By using memory-specified network interconnects, area overhead of network interconnects for the memory chip is reduced by 63% and the latency overhead by 43%. Signal lines between the two chips are directly connected by 10-mu m-pitch inter-chip electrodes, resulting in fast and low-energy inter-chip transmission.

• 出版日期2010-1