A Memory-Efficient Scalable Architecture for Lifting-Based Discrete Wavelet Transform

作者：Hu Yusong^*; Jong Ching Chuen

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2013, 60(8): 502-506.

DOI：10.1109/TCSII.2013.2268335

• Discrete wavelet transform (DWT)
• lifting scheme
• parallel 2-D DWT architecture
• systolic array

In this brief, we propose a new parallel lifting-based 2-D DWT architecture with high memory efficiency and short critical path. The memory efficiency is achieved with a novel scanning method that enables tradeoff of external memory bandwidth and on-chip memory. Based on the data flow graph of the flipped lifting algorithm, processing units (PUs) are developed for maximally utilizing the inherent parallelism. With S number of PUs, the throughput can be scaled while keeping the latency constant. Compared with the best existing architecture, the proposed architecture requires less memory. For an N x N image, the proposed architecture consumes a total of only 3N + 24S words of transposition memory, temporal memory, and pipeline registers. The synthesized results in a 90-nm CMOS process show that it achieves better area-delay products than the best existing design by 32.3%, 31.5%, and 27.0% when S = 2, 4, and 8, respectively, and by 26%, 26%, and 22% when the overhead for buffering the required overlapped pixels is taken into account.

• 出版日期2013-8
• 单位南阳理工学院