摘要
In this paper, a methodology for the power-optimal design of high-resolution low-bandwidth switched-capacitor Sigma Delta modulators (Sigma Delta Ms) is presented. The most power-efficient Sigma Delta architecture is identified among single-loop feedback and feed-forward topologies with different loop orders N, oversampling ratios OSR, and quantizer resolutions B. Based on this study, an experimental prototype has been implemented in a 0.18-mu m CMOS process. It achieves a signal-to-noise ratio of 95 dB over a signal bandwidth f(BW) of 10 kHz. The prototype operates with a 1.28-MHz sampling rate and consumes 210 mu W from a 1.8-V supply.
- 出版日期2012-11