摘要

Further power and energy reductions via technology and voltage scaling have become extremely difficult due to leakage and variability issues. In this paper, we present a robust and energy-efficient computation architecture exploiting an asynchronous timing strategy to dynamically minimize leakage and to self-adapt to process variations and different operating conditions. Based on a logic topology with built-in leakage suppression, the prototype asynchronous neural signal processor demonstrates robust sub-threshold operation down to 0.25 V, while consuming only 460 nW in 0.03 mm(2) in a 65 nm CMOS technology. These results represent a 4.4x reduction in power, a 3.7x reduction in energy and a 2.2x reduction in power density, when compared to the state-of-the-art processors.

  • 出版日期2013-4