A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI

作者：Kwak Jaehwa^*; Nikolic Borivoje

来源：IEEE Journal of Solid-State Circuits, 2016, 51(10): 2368-2379.

DOI：10.1109/JSSC.2016.2582860

• Adaptive clocking
• dynamic frequency scaling
• energy-efficient processor
• delay-locked loop (DLL)
• tunable replica circuit (TRC)
• Metastability
• FDSOI

This work demonstrates a self-adjustable clock generator that closely tracks the voltage dependence of the critical path delay in a microprocessor. A tunable replica circuit (TRC) composed of inverter cells from the standard-cell library performs real-time frequency modulation to reduce the response time to a single cycle, and a digital controller quantizes the clock frequency by selecting appropriate phases of a delay-locked loop (DLL) that generates 16 phases of 2 GHz output. A watchdog unit continuously monitors the clock output to guard against metastability arising from the asynchronous path between the controller and the DLL. The proposed design is implemented in a 28 nm UTBB FDSOI technology and occupies an area of 1120 mu m(2) with 2.7 mW power consumption. The generator has a wide tuning range of 550-2260 MHz at 1 V, functions at 35 MHz at 0.4 V, and can continuously synthesize the clock signal for arbitrary voltage waveforms between 0.4 V and 1 V.

• 出版日期2016-10