Design Requirements for Steeply Switching Logic Devices

作者：Kam Hei^*; Liu Tsu Jae King; Alon Elad

来源：IEEE Transactions on Electron Devices, 2012, 59(2): 326-334.

DOI：10.1109/TED.2011.2175484

• Low power electronics
• subthreshold slope
• transistor
• 60 mV/dec

Many steeply switching logic devices have recently been proposed to overcome the energy efficiency limitations of CMOS technology. In this paper, circuit-level energy-performance analysis is used to derive the design requirements for these alternative switching devices. Using a simple analytical approach, this paper shows that the optimal I-on/I-off and E-dyn/E-leak ratios are set only by circuit-level parameters as well as the device transfer characteristic OFF-state S-off, ON-state S-on, and effective S-eff inverse slopes. For a wide variety of switching device characteristics and circuit parameters, the optimal E-dyn/E-leak ratio is approximately (K/2)(S-eff/S-off) - 0.56(S-on/S-off) - 0.56, where K ranges from 6.23 to 11.9. Based upon this theoretical framework, simple requirements for S-off, S-on, and S-eff are established in order for an alternative switching device to be more energy efficient than a MOSFET. The results reemphasize that merely focusing on achieving the steepest local inverse slope S is insufficient, since energy dissipation is set mainly by S-eff and not by S. Finally, the general shape of the energy-delay curve is also set by these inverse slopes, with its steepness directly proportional to S-on/S(of)f. This analytical approach provides a simple method to assess the promise of any new device technology in potentially overcoming the energy efficiency limitations of CMOS technology.

• 出版日期2012-2