摘要

Over the past few years, metal gates and high-k gate dielectrics have been intensively developed to implement sub 50nm CMOS technology. Nevertheless, some issues of metal gate and high-k gate dielectric need to be solved. In particular, the high density of traps in dielectric and workfunction modulation with metal gate should be addressed by either understanding the mechanism or developing a new process. In this paper, we propose an analyses method and various processes to understand and solve the problems of metal gate and high-k gate dielectrics. First, to effectively passivate high-k/Si interface traps, post metallization annealing in high pressure hydrogen ambient was investigated. Compared with conventional forming gas annealing, high pressure annealing showed improved device performance owing to the effective passivation of interface traps. Second, the effect of traps in the high-k layer was evaluated by single pulsed I-d-V-g measurement and reliability such as bias temperature instability. By using nano-scale analysis, we have confirmed that non-uniform oxygen vacancy causes charge trapping and reliability degradation. Then, the interaction of metal gate and gate dielectric during thermal process was investigated with various metal electrodes and systems. Metal/dielectric interaction was found to be severe in elemental and ternary metal electrodes, while the binary metal electrode showed minimum interaction. To achieve appropriate workfunction with minimal interaction, the bi-layer metal electrode and conducting oxide electrode were developed. Both electrodes showed suitable workfunction which is close to conduction and valance band of silicon with improved thermal stability.

  • 出版日期2007-6