An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS

作者：Suemesaglam Taner

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2014, 61(4): 219-223.

DOI：10.1109/TCSII.2014.2305217

• Analog front end
• analog integrated circuits
• CMOS
• dynamic linear equalizer
• equalization
• Graphics Double Data Rate (GDDR)
• high-speed I/O
• memory interface
• receiver
• single-ended

A receiver circuit employing a dynamic linear equalization technique is presented. The new circuit method removes the traditional continuous-time linear equalizer (CTLE) and builds equalization into strong-arm latches (SALs). Fabricated in a 22-nm CMOS technology, the receiver's performance is experimentally verified at 11 Gb/s with better than bit error rate 10(-12) at 0.17 mW/Gb/s power efficiency, which advances the state of the art. The power efficiency is 55% better than the CTLE alternative on the same silicon. Analysis and simulation methods for the dynamic linear equalization and other architectural details are also presented.

• 出版日期2014-4