A 12 b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC

作者：Lee Sunghyuk^*; Chandrakasan Anantha P; Lee Hae Seung

来源：IEEE Journal of Solid-State Circuits, 2012, 47(7): 1603-1614.

DOI：10.1109/JSSC.2012.2191184

• Analog-to-digital conversion (ADC)
• calibration
• pipeline
• scalability
• switched-capacitor circuits
• voltage scaling
• zero-crossing
• zero-crossing based circuits (ZCBC)

A voltage scalable zero-crossing based (ZCB) pipelined ADC built in 65 nm CMOS is described. The highly digital implementation characteristic of the ZCB circuit technique enables energy efficient operation and supply voltage scaling. Several new techniques including the unidirectional coarse-fine charge transfer scheme, programmable ramp rates, and flash resistor ladder scaling, are developed to allow efficient operation at different supply voltages as well as to extend the supply voltage range down to 0.5 V. Two versions, the first fabricated in 65 nm GP (general purpose) technology, and the second in 65 nm LP (low power) technology from an identical design file show similar performance characteristics except for the power supply voltage ranges, demonstrating the robustness of the design. At 1.0 V (GP)/1.2 V (LP) nominal supply and 50 MS/s, the ADC achieves 67.7 dB (GP)/68.1 dB (LP) SNDR after calibration while dissipating 4.07 mW (GP)/4.93 mW (LP), resulting in an FOM of 41.0 fJ/step (GP)/47.5 fJ/step (LP). The supply voltage scalability is demonstrated down to 0.5 V (GP)/0.8 V (LP) and improves the FOM to 28.0 fJ/step (GP)/37.8 fJ/step (LP), while maintaining higher than 66 dB SNDR.

• 出版日期2012-7