A Substrate-Dissipating (SD) Mechanism fora Ruggedness-Improved SOI LDMOS Device

作者：Wang, Bing; Wang, Zhigang^*; Kuo, James B.

来源：IEEE Journal of the Electron Devices Society, 2018, 6(1): 739-746.

DOI：10.1109/JEDS.2018.2831278

• Unclamped inductive switching (UIS)
• SOI LDMOS
• avalanche current
• parasitic BJT
• substrate-dissipating (SD)
• self-heating

An SOI LDMOS device with improved ruggedness under unclamped inductive switching (UIS) is described based on the substrate-dissipating (SD) mechanism. The key feature of this device is the introduction of a Gamma-shape P-island window with a relatively high doping concentration to connect the N-drift region to the P-substrate under the source, which is designed to achieve an avalanche breakdown point at the edge of the P-island instead of near the gate contact. Thus, the avalanche current is shortened to the substrate contact through the P-island and the P-substrate, avoiding the avalanche current to pass through the N+ source/P-well junction and thus suppressing the activation of the parasitic bipolar transistor with a relaxed self-heating effect especially in the P-well region. As verified by the Medici device simulation results, the SD mechanism of the device under the UIS condition, may endure a remarkably higher avalanche current as compared with the conventional SOI LDMOS device.

• 出版日期2018
• 单位西南交通大学