A novel low power time-mode comparator for successive approximation register ADC

作者：Kobenge Sekedi B^*; Yang Huazhong

来源：IEICE Electronics Express, 2009, 6(16): 1155-1160.

DOI：10.1587/elex.6.1155

• time-mode comparator
• current starved inverter
• time-to-voltage converter
• analog-to-digital converter

A novel low power time-mode comparator with enhanced resolution and speed is proposed in this paper. The comparator incorporates a symmetrical input time-to-digital converter (TDC) and a highly dynamic voltage-to-time converter (VTC). Energy reduction is achieved mainly through the use of capacitor discharge automatic switch-off and inverter clocking. The combined effect of the low timing requirement and capacitor voltage presetting enables significant precision and speed improvements. Simulations in a 0.18 um process show that the comparator can be clocked at 38 MHz, draws less than 0.4 pJ energy from supply and can resolve voltages as low as 10 mu V.

• 出版日期2009-8-25
• 单位清华大学