A low noise clock generator for high-resolution time-to-digital convertors

作者：Prinzie J^*; Christiaensen J; Moreira P; Steyaert M; Leroux P

来源：Journal of Instrumentation, 2016, 11(02): C02038.

DOI：10.1088/1748-0221/11/02/C02038

• VLSI circuits
• Analogue electronic circuits
• Radiation-hard electronics
• Digital electronic circuits

A robust PLL clock generator has been designed for the harsh environment in high-energy physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 MHz and performs a multiplication by 64. An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz up to 3.2 GHz with internal discrete bank switching. The PLL includes an automatic bank selection algorithm to correctly select the correct range of the oscillator. The PLL has been fabricated in a 65 nm CMOS technology and consumes less than 30 mW. The additive jitter of the PLL has been measured to be less than 400 fs RMS.

• 出版日期2016-2