A Study of Self-Dithering for Delta Sigma Fractional-N PLL

作者：Kato Yuji^*; Ioka Eri; Matsuya Yasuyuki

来源：Electronics and Communications in Japan, 2015, 98(1): 9-14.

DOI：10.1002/ecj.11606

• PLL
• fractional-N
• sigma modulator
• limit cycle
• dithering

The sigma fractional-N phase-locked loops (PLL) are being investigated in order to realize a low fractional spurious signal characteristic. In this PLL, the sigma modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the sigma modulator when the input value is fixed, and as a result, the limit cycle oscillation increases the spurious signal power. Therefore, a method is required to suppress this oscillation. In this paper, we propose a self-dithering sigma fractional-N PLL that inhibits the limit cycle oscillation without an external dither generating circuit. The proposed circuit generates dither from the internal signals of the PLL. We simulated the output spectrum of the proposed circuit. The results showed that the proposed circuit suppressed limit cycle oscillation, and that the spurious level of the proposed circuit was almost equal to the spurious level without limit cycle oscillation.

• 出版日期2015-1