A cost-effective wafer-level reliability test system for integrated circuit makers

作者：Tseng, SFC^*; Chien, WTK; Gong, E; Cai, BC

来源：IEEE Transactions on Instrumentation and Measurement, 2003, 52(5): 1458-1467.

DOI：10.1109/TIM.2003.818543

• automatic testing equipment (ATE)
• integrated circuit (IC)
• reliability
• semiconductor test
• wafer-level reliability (WLR)

Wafer-level reliability (WLR) testing receives much attention and becomes a major tool for process reliability qualification and in-line monitoring because WLR can provide real-time results for timely improvements. This in-situ test capability is greatly attributed to an automatic parametric tester for sample handling and data collection/analysis. This paper presents a cost-effective WLR test system for a semiconductor maker (an IDM as well as a foundry). The proposed system consists of flexible and extensible algorithm generation, which helps realize low-cost WLR solutions. The key features of our proposed system include cost-effective instrumentation (i.e., an Agilent 4156C parameter analyzer, a semi-auto, and thermal CASCADE 12751 wafer prober, a pulse generator, and a switching matrix) and the software for interface control and data analysis. Compared with the corresponding automatic test equipment (ATE), our system is capable of measuring electrical characteristics with higher accuracy and a wider temperature range. This leads to significant cost saving, much enhanced tool utilization, and improved flexibility. Its great extensibility is especially important for a wafer foundry, which often suffers test capacity shortage when numerous verifications and qualifications are to be done.

• 出版日期2003-10
• 单位上海交通大学