A 0.5 V offset cancelled latch comparator in standard 0.18 mu m CMOS process

作者：Khanghah Meysam Mohammadi^*; Sadeghipour Khosrov Dabbagh

来源：Analog Integrated Circuits and Signal Processing, 2014, 79(1): 161-169.

DOI：10.1007/s10470-013-0239-z

• Latch comparator
• Low voltage circuits
• Offset cancellation
• Speed up technique
• Standard CMOS process
• 0.5 V circuits

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 mu m standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 mu V before and after offset cancellation, respectively. The designed comparator dissipates 34 mu W power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.

• 出版日期2014-4