摘要

Based on charge conservation assumption, analytical models of the drain-induced grain barrier lowering effect are developed for polysilicon films by J-D Poisson's equation and for polysilicon thin-film transistors (poly-Si TFTs) by quasi-2-D Poisson's equation. It is shown that the voltage drop at the lower barrier side is less than that at the higher barrier side for both poly-Si films and poly-Si TFTs when applying a lateral bias across the grain-boundary barrier.