An 8.5 mW Continuous-Time Delta Sigma Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR

作者：Kauffman John G^*; Witte Pascal; Becker Joachim; Ortmanns Maurits

来源：IEEE Journal of Solid-State Circuits, 2011, 46(12): 2869-2881.

DOI：10.1109/JSSC.2011.2164303

• Analog-to-digital conversion
• background correction
• continuous-time
• DAC error estimation
• delta-sigma modulation
• DS modulation
• finite gain-bandwidth compensation
• low power design
• multibit DAC linearization
• multibit internal quantization
• SD modulation
• sigma-delta modulation

This paper presents a third order, single-loop, continuous-time Delta Sigma modulator with an internal 4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of only 10. Therefore, DAC linearization by dynamic element matching is ineffective, and the DAC nonlinearities are not corrected within the Delta Sigma modulator loop but in the subsequent digital circuit. The unit element mismatches are digitally estimated based on a correlation, and correction factors are thus derived. Moreover, in order to achieve a low-power operation, all amplifiers are compensated for finite gain-bandwidth related non-idealities. In the presented work, this compensation includes the fast proportional loop, which is used to compensate for excess loop delay. The presented Delta Sigma modulator has been realized in a 1.2 V, 90 nm CMOS process and achieves an SNDR of 63.5 dB and an SFDR of 81 dB within a 25 MHz bandwidth. The modulator occupies an active die area of only 0.15 mm(2) and has a power consumption of 8mW, with an additional 0.02 mm(2) and 0.42 mW estimated for the digital DAC correction logic. The overall modulator achieves a figure of merit of 138 fJ/conv.

• 出版日期2011-12