An efficient hardware implementation of a novel unary Spiking Neural Network multiplier with variable dendritic delays

作者：Diaz Carlos^*; Sanchez Giovanny; Duchen Gonzalo; Nakano Mariko; Perez Hector

来源：Neurocomputing, 2016, 189: 130-134.

DOI：10.1016/j.neucom.2015.12.086

• FPGA
• Unary multiplier
• Dendritic delays
• Neuromorphic

We propose a novel unary spiking circuit for a serial multiplier with variable dendritic delays. Serial multipliers commonly use the soma model for the arithmetic operation. The structure of the serial multiplier and the efficient implementation of the dendritic delays on customized neuromorphic hardware are the major contributions of this work. The design of the multiplier was inspired by the biological processes of dendrites, which use feedback connections and dendritic growth to synchronize the neural processing performed by the soma. The multiplier eliminates complex rules by adopting the soma model with dendritic connectivity configurations, increasing the processing speed compared with previously reported solutions based on Spiking Neural Networks.

• 出版日期2016-5-12