科研之友
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摘要
This paper proposed an efficient phase-locked loop (PLL) that features zero steady-state error of phase and frequency under voltage sag, phase jump, harmonics, DC offsets and step-and ramp-changed frequency. The PLL includes the sliding Goertzel discrete Fourier transform (SGDFT) filter-based fundamental positive sequence component separator (FPSCS), the synchronous-reference-frame PLL (SRF-PLL) and the secondary control path (SCP). In order to obtain an accurate fundamental positive sequence component, SGDFT filter is introduced as it features better filtering ability at the frequencies that are integer times of fundamental frequency. Meanwhile, the second order Lagrange-interpolation method is employed to approximate the actual sampling number including both integer and fractional parts as grid frequency may deviate from the rated value. Moreover, an improved SCP with single-step comparison filtering algorithm is employed as it updates reference angular frequency according to the FPSC, which promises a zero steady-state error of phase and improves the frequency tracking speed. In this paper, the mathematical model of the proposed PLL is constructed, its stability is analyzed. Also, design procedure of the control parameters is presented. The effectiveness of the proposed PLL is confirmed by experimental results and comparison with advanced pre-filtering PLLs.
