An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits

作者：Huang Yi Chieh^*; Wang Ping Ying; Liu Shen Iuan

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2012, 59(3): 148-152.

DOI：10.1109/TCSII.2012.2184378

• All-digital
• clock and data recovery
• jitter tolerance

An all-digital on-chip jitter tolerance measurement technique for clock/data recovery (CDR) circuits is presented. A 6-Gbps CDR circuit with this proposed technique is realized in a 90-nm CMOS process. The measured jitter tolerance by using the testing equipment and the proposed technique correlate within 13% in the frequency range of 178 kHz similar to 11.3 MHz. The measured peak-to-peak data and clock jitters are 15.56 and 13.3 ps. The power of the CDR circuit is 44.4 mW at a supply voltage of 1.2 V.

• 出版日期2012-3
• 单位中国科学院电工研究所