摘要

This paper presents a novel technique to shape feedback DAC mismatch without any extra digital elements inside the sigma-delta loop by inserting an analog integrator and an out-of-loop digital differentiator. To lower power dissipation, a novel triple integrator with low capacitor mismatch sensitivity of the delay paths is proposed. As a result, the SDM with three integrators is realized by only one OTA. The proposed topology, simulated at transistor level on 0.13 mu m CMOS process, achieves 98.4 dB SNDR with 100 kHz bandwidth and 1.2 mW power dissipation from a single 1.2 V supply voltage. Its specification satisfies the GSM requirements.